library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity tb_incrementer is
end tb_incrementer;

architecture BEH of tb_incrementer is
    component incrementer
        Port ( X : in  STD_LOGIC_VECTOR(7 downto 0);
               F : out  STD_LOGIC_VECTOR(7 downto 0));
    end component;

   signal X_test : STD_LOGIC_VECTOR(7 downto 0) := "00000000";
   signal F_test : STD_LOGIC_VECTOR(7 downto 0);

begin
    uut: incrementer port map (
        X => X_test,
        F => F_test
    );

    process
    begin
        wait for 10 ns;
        X_test <= "00000000";
        wait for 10 ns;
        assert F_test = "00000001" report "Increment failed for 0" severity error;
        
        X_test <= "00000001";
        wait for 10 ns;
        assert F_test = "00000010" report "Increment failed for 1" severity error;
        
        X_test <= "11111111";
        wait for 10 ns;
        assert F_test = "00000000" report "Increment failed for max value" severity error;
        
        X_test <= "10000000";
        wait for 10 ns;
        assert F_test = "10000001" report "Increment failed for middle value" severity error;
        
        wait;
    end process;
end BEH;